00:00/00:00
您的浏览器不支持 audio 标签。
Listen to this article
1x
Huawei's Ascend 910 series AI chips in Hangzhou on May 10, 2026. Photo: VCG
Huawei Targets 1.4-Nanometer Chip Performance by 2031 With New Design Architecture
The Chinese tech giant said its “Tau Scaling Law” can boost chip efficiency through vertically stacked circuit design
TL;DRAI
Huawei targets 1.4nm chip performance by 2031 via Tau Scaling Law: vertical stacking to cut signal latency, no transistor shrinkage required. A credible U.S.-curbs bypass that puts Ascend on the AI accelerator shortlist for enterprises with China exposure.
118 words~1 min read
