(Image credit: Intel)
The race is on to build the massive chip packages that power the future of AI, with some technologies being developed to produce a single chip that houses a monstrous 58 chips in one unit. But the future pathway to those sorts of massive chips isn't entirely agreed upon yet, as learned at TSMC's recent European Technology Symposium that we attended.Although panel-level packaging technologies are set to enable much larger chip packages, they will not provide, at least initially, the same interconnection densities as today's wafer-level packaging technologies like CoWoS, according to Kevin Zhang, TSMC’s senior vice president of business development and global sales and deputy co-COO."The geometry complexity panel-based process has to deal with is nowhere near the wafer level technology capability," Zhang said. "CoPoS, I would say it is one way to basically using panel-based process to continue driving the interposer scaling."One of the common misconceptions in the semiconductor industry is that panel-based chip packaging technologies will replace existing wafer-based technologies like CoWoS as they promise to enable considerably larger package sizes — think 310mm×310mm, up from existing 120mm×150mm — at lower costs. This is not the case, though, according to TSMC."That is an option on the table," Zhang said. "But remember, if you look at our CoWoS roadmap, we still have a lot of runway left with wafer-level technologies. We can scale CoWoS all the way to 14X using wafer-level processes, and we also have wafer-level integration. […] You can integrate 58 large reticle-sized dies together. So, there is still plenty of room for us to continue advancing wafer-level integration. At the same time, our team always wants to make sure we evaluate all future options. Obviously, one of those options is panel-based packaging."
