IBM Research has unveiled NanoStack, a sequential stacking CMOS transistor architecture that essentially builds chips upward like skyscrapers rather than sprawling them outward like suburbs. The design targets what the company calls the CMOS 7A node and beyond, promising roughly 50% area scaling compared to IBM’s existing 2 nm technology.
What NanoStack actually does
The architecture introduces several innovations that distinguish it from prior approaches to vertical chip integration. NanoStack allows flexible positioning of top and bottom nanosheet channels, meaning engineers can optimize where transistors sit within the stack based on performance requirements rather than being locked into rigid configurations.
It also features a thermally stable bottom FET gate stack. This has historically been one of the hardest problems in stacking transistors vertically, because building new layers on top of existing ones subjects everything below to additional thermal stress.
Thin dielectric bonding ties the layers together, creating what IBM describes as a manufacturable sequential multi-channel approach.
