FIRST LOOK: IBM is once again testing the limits of chip design, this time with an architecture that moves beyond traditional scaling into a more three-dimensional layout aimed at AI workloads. The company refers to the design as a "nanostack" architecture and says it can fit nearly 100 billion transistors onto a chip roughly the size of a human fingernail. That's roughly double the density of IBM's last generation, but the bigger story is how it gets there.
Rather than continuing to shrink components along a flat plane, IBM is stacking transistors vertically. That change comes as semiconductor designers run up against the physical limits of traditional scaling, making further miniaturization increasingly difficult and less efficient.
In a media briefing covered by Ars Technica, IBM describes the breakthrough as the "world's first sub-1-nanometer chip technology" for AI data centers, though the label is more about performance expectations than literal dimensions. Node names have not corresponded to physical measurements for years. Here, IBM is basically saying the chip behaves like a true sub-1-nanometer design, even though its physical features aren't that small.
"It's not just an incremental step, it's a meaningful leap forward," said Jay Gambetta, director of IBM Research and IBM Fellow, in the briefing. He described the new chip technology as "pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy."
