(Image credit: SK Hynix)
SK hynix doesn't expect hybrid bonding to be ready for HBM4E, Jaesik Lee, VP of package engineering at SK hynix America, said during a presentation at Hot Chips 2026 on August 23, pushing the industry's most anticipated memory packaging transition out to HBM5 at the earliest.The problem, as he describes it, is that HBM cubes are capped at a total thickness of 775 microns — the standard thickness of a 300mm logic wafer — so every additional DRAM layer must come from thinner dies and narrower gaps. 16-Hi HBM4, now in customer qualification at 48GB per cube while 12-Hi is in mass production, thins its core dies to around 50 microns and halves the gap between them compared with 12-Hi. Lee's session also went into detail about the company's iHBM cooling architecture three months after its May unveiling. Attaching a constraint to it, Lee explains that the heat blocks can't be applied to any HBM generation already in design.
(Image credit: SK Hynix)The 775-micron limitThe JEDEC HBM4 standard raised the package thickness ceiling from 720 microns, which held through HBM3E, to 775 microns, easing the pressures associated with adopting hybrid bonding. When a GPU package gets its cold plate attached, both the logic die and the memory stacks are ground back to expose bare silicon, Lee said, and because logic wafers are 775 microns thick, a memory cube that grew any taller would stand proud of the processor beside it. "That's the kind of limit that we can go up so far, because the logic wafer thickness is also 775 microns," Lee said.Thinner dies leave the stack with proportionally more oxide, which conducts heat poorly compared with silicon, while pin speeds that have risen from 1 Gbps in early HBM to 8 Gbps in HBM4 concentrate more power in the same footprint. SK hynix's own figures put the thermal burden at 2.2 times higher across the HBM generations shown, while stack counts double every two generations.
