TSMC's CoPoS Packaging Aims to Break the AI Chip Size Limit by 2028

The next limit on AI chips lies past the transistor in the package that holds everything together, and TSMC has named its answer. The company is preparing CoPoS, or chip-on-panel-on-substrate, a packaging method that swaps the round silicon wafer for a large rectangular panel, with mass production set for the second half of 2028. The analyst Ming-Chi Kuo expects Nvidia's Feynman accelerator, the chip after Rubin, to be the first major product built on it. The shift matters because packaging, once an afterthought, now decides how big and how cheap an AI chip can be.

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