(Image credit: SMIC)
An analysis of Huawei's Kirin 9030 system-on-chip (SoC) for smartphones conducted by SemiAnalysis revealed that SMIC's third-generation 7nm-class fabrication technology (N+3) has smaller metal pitch than Intel's 18A fabrication technology and that China's leading foundry has managed to achieve transistor density on par with manufacturing process that rely on EUV lithography. But does this make SMIC's N+3 node as competitive as Intel's 18A or TSMC's N2 and N3? Not really.Go deeper with TH Premium: ChipmakingSemiAnalysis' teardown indicates that SMIC's N+3 fabrication process supports a minimum metal pitch of 32.5nm, which is nominally tighter than the approximately 36nm pitch used for many high-performance cells in Intel's Panther Lake CPU, even though 18A can support approximately 32nm metal pitches. The video from SemiAnalysis and High Yield does not reveal other important characteristics of SMIC's N+3, such as contacted gate pitch (CGP), standard cell height (tracks or nm), or fin pitch, so we cannot make direct comparison of this node to Intel's or TSMC's technologies. What it does reveal is estimated transistor density of around 113.4 million transistors per square millimeter (Mtr/mm2), which is even higher than transistor density of TSMC's N6, 107.7 Mtr/mm2.TSMC's N6 uses multiple EUV layers, so achieving higher transistor density without using EUV lithography is an indisputable technological achievement of SMIC. The foundry achieves this density by using DUV multi-patterning, including self-aligned quadruple patterning on the tightest layers, and extensive design-technology co-optimization (DTCO). In addition, SemiAnalysis believes that SMIC used techniques like reduced fin counts, placing contacts directly over active gates, and tightening cell isolation. Such methods allow for increased transistor density, but at the cost of increased process complexity, cost, yield risks, and design constraints.
