IBM has built a new prototype chip with around 100 billion transistors on an area the size of a fingernail, which is twice the density of the company’s previous state-of-the-art technology announced in 2021. The design could pave the way for faster and more energy efficient computers for years to come. For more than half a century, chipmakers have been able to make ever more powerful computers by following the key principle of Moore’s Law: cram more transistors onto the chip. To do this, they shrank transistors—the tiny switches that perform computations—to incrementally smaller sizes. But in the last fifteen years, transistors have gotten close to the limit where quantum mechanics starts to interfere with their function: just a few dozen nanometers in size. They can’t get smaller. So to fit more transistors on a chip, engineers across the industry are eyeing a pivot to an approach familiar to urban planners: build up. On Thursday, IBM announced it created a chip that uses this strategy. The new architecture, known as a nanostack, vertically stacks transistors in two layers on a silicon chip. “It's not just an incremental step,” Jay Gambetta, the director of IBM Research, said during a press conference on Tuesday. “It's a meaningful leap forward.” Within a decade, Gambetta expects chips with nanostacking to be widely used in data centers, where their improved efficiency could help the facilities better manage their energy consumption.