The AI boom has a bottleneck problem, and it’s not compute. It’s memory. DRAM prices doubled in Q1 2026, high-bandwidth memory is sold out through at least 2027-2028, and every major chipmaker is scrambling for wafer capacity. Into this chaos walks Kepler Computing, a Moraga, California startup claiming its ferroelectric RAM technology can fundamentally change how chips handle data.
The US Department of Commerce apparently agrees with the pitch. On July 29-30, the agency unveiled a letter of intent to award Kepler up to $245 million under the CHIPS Act, earmarked for research and development of high-performance AI memory. The funding is part of a broader $874 million allocation spread across seven companies, with the government set to take a minority equity stake as part of the deal.
What Kepler is actually building
Traditional chip architectures shuttle data back and forth between memory and processors, a design limitation known as the von Neumann bottleneck. Kepler’s approach stacks ferroelectric RAM tiles directly on top of computational logic chips using 3D heterogeneous integration. The company’s ferroelectric RAM uses materials like hafnium zirconium oxide to store data, and peer-reviewed research published in April 2026 demonstrated that this architecture can be manufactured using existing CMOS processes.
