XCENA Details MX1 Architecture Integrating Memory Expansion and Near-Memory Computing at Hot Chips 2026
Single CXL Type 3 device combines up to 2 TB of DDR5, SSD-backed capacity and 1,000+ RISC-V cores
Benchmark tests show up to 4.7x the throughput and 18.7x the energy efficiency of host CPU processing over CXL on selected data-analytics kernels
XCENA, a semiconductor company developing memory-centric computing solutions for AI infrastructure, today presented the architecture and measured performance of MX1, its computational CXL memory architecture, during the Hot Chips 2026 Memory session. Presented by Harry Kim, Chief Product Officer of XCENA, the session examined how MX1 combines large-scale memory expansion, SSD-backed capacity and programmable near-memory computing in a single CXL Type 3 device to address the growing memory constraints of AI infrastructure.
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