(Image credit: Getty Images / Bloomberg)
This Tom's Hardware Premium article is free to read with a Tom's Hardware account; no payment necessary. We're offering free access from August 23 to 26 so you can read all of our reporting from Hot Chips.Raghu Sreeramaneni, Micron HBM Design Architecture Fellow, told the Hot Chips 2026 conference on August 23 that the silicon penalty HBM carries against DDR5 is growing with every generation, and that it can’t be closed without giving up performance, something that Micron won’t do. Pressed on whether newer parts narrow the gap, he said it’s "definitely not getting better," putting the current overhead at roughly three times the wafer area of DDR5 for the same capacity. That trajectory is the reason why PC memory hit record prices this year, with conventional DRAM contract prices up 90% to 95% quarter over quarter in the first quarter of 2026.
(Image credit: Micron)Wafer mathematicsAn HBM4 die fits 256 banks against 32 on a DDR5 die, and it reaches its bandwidth by running those banks in parallel, which requires far more die area for data paths, power delivery, and the through-silicon vias (TSVs) that link each layer to the base die. A single HBM3E die can feed 256 GB/s, while one DDR5 die supplies about 8 GB/s, so matching a given bit count makes the HBM die much larger.Micron has publicly put that overhead at about three times the wafer area of DDR5, and Sreeramaneni said it traces to an HBM3E-against-DDR5 comparison that grows with each generation as pin speeds, bank counts, stack heights, and die sizes climb higher. He called HBM "probably the most cross-functionally complex solution that we make," and noted that in a two-GPU package, memory accounts for around 90% of the silicon, roughly eight times the area of the GPU dies. HBM already sells for about five times the price of DDR5 per bit, so each wafer a maker moves to it removes a disproportionate share of commodity memory from the market, pushing consumer product prices higher as a consequence.
