TIER IV joins JST's Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving

TIER IV joins JST's Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for…

TIER IV joined JST's R&D program to design and open-source an AI chip for Level 4 autonomous driving on Autoware, with optimized Transformer inference. Open-sourcing chip logic, compiler, and TOSA toolchain enables OEMs to integrate flexible AI frameworks and accelerate autonomous SoC commercialization independently.