Altera and Riverlane Partner on QEC Interfaces for Agilex FPGAs Following Post-Quantum Security Rollout - Quantum Computing Report

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Altera and Riverlane Partner on QEC Interfaces for Agilex FPGAs Following Post-Quantum Security Rollout

FPGA provider Altera (an Intel company) and quantum error correction (QEC) specialist Riverlane have announced a partnership to optimize real-time QEC data movement and low-latency control logic across Altera’s Agilex® FPGA portfolio. Under the agreement, Riverlane joined the Altera Solutions Acceleration Partner (ASAP) Program and validated its open-source QEC Interface (QECi) protocol on Altera Agilex 7 devices, establishing a standardized data-interchange framework between quantum control electronics and physical QEC decoders.