RUMOR MILL: Intel is betting on large caches to boost performance in its next desktop lineup, and new details show that approach extending into the midrange. Those details come from a post by well-known Intel leaker Jaykihn, who says Intel is working on two Core Ultra 5 400S chips based on the upcoming Nova Lake-S platform. Both CPUs are described as 22-core designs built on a single compute tile, aimed at mainstream desktops, including gaming-focused rigs.
According to the post, each processor combines 6 "Coyote Cove" P-cores, 12 "Arctic Wolf" E-cores, and 4 LP-E cores. That mix suggests a design that balances compute throughput with background and low-power tasks, rather than just piling on more performance cores.
The standout detail in the updated specs is the cache. Intel is said to be attaching a large block of big Last Level Cache, or bLLC, to these chips.
The bLLC adds 108 MB on top of the standard cache, and the configuration can expose up to 144 MB of bLLC, according to the leak. The approach echoes AMD's X3D models, but the scale suggests Intel is pushing cache size even more aggressively in these particular midrange parts.
The aim is to keep more data on the chip and closer to the cores. In gaming and other latency-sensitive tasks, performance often depends less on raw core count and more on how quickly the CPU can access the data it needs from memory.
