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IQM Quantum Computers Minimizes Qubit Footprint via Planar Directional Tile Codes
Superconducting hardware developer IQM Quantum Computers has introduced a quantum error correction (QEC) architecture termed directional tile codes. Co-authored with academic teams at Freie Universität Berlin, the University of Edinburgh, and Johannes Gutenberg-Universität Mainz, the research outlines a framework to implement high-rate Quantum Low-Density Parity-Check (qLDPC) codes on standard, two-dimensional planar processor layouts. By validating these error-correcting codes on a strictly planar grid, the approach reduces the physical physical-to-logical qubit overhead up to 1,000 times compared to traditional surface codes, bypassing the need for long-range couplers, three-dimensional vertical routing lines, or complex physical mechanical qubit shuttling mechanisms.
