Registers, Lanes, and Berry Phase: Lifting Siunertaq from Batch Graphs to the Complex Plane

The previous article is here: Mainframes, Monads, and Stack Machines: Extending Siunertaq to the Batch Layer

This is the second follow-up to Dhall-to-Effect and provably safe task orchestration and Mainframes, Monads, and Stack Machines. The short version of both: we model build graphs as norm-bounded quivers, verify them with Z3/Yices before any effect fires, and orchestrate steps using JCL-inspired ADTs backed by Dhall and Spring Batch + Pekko.

The previous posts worked at the graph level: vertices, edges, the shape of dependencies. This one goes one level down — to registers.

The insight that forced this descent was noticing that Ref[IO, Array[Byte]] is a dangerous type: anyone who calls .get holds a mutable alias to the array and can change its contents without going through the Ref. We needed something with the guarantees of a GPU register file: fixed width, typed, atomically updated, never aliased. That observation turned out to connect directly to SIMD/SIMT architecture — and from there, to complex Berkovich heights and braid group theory.

Here is how it unfolded.