FIRST LOOK: AMD's next-generation Epyc Venice server chip has begun its production ramp on TSMC's N2 node, the foundry's new 2nm-class process. That move brings a 256-core server part onto one of the most advanced nodes at a time when data centers are straining to add capacity for AI and other agentic workloads.
Venice is a 6th-gen Epyc chip based on the Zen 6 core architecture and targeted at dense data center workloads. AMD is claiming more than a 70% improvement in overall performance and efficiency versus the current Epyc Turin chips, along with more than a 30% increase in thread density.
The extra performance is not just from adding cores; AMD is also leaning on IPC improvements, higher clocks, and changes in the core and uncore design to close the gap. The lineup is expected to include a 96-core part and a much denser 256-core, 512-thread model, lifting the top core count by about one-third over Turin's 192-core, 384-thread ceiling.
The Venice platform is designed to keep those cores and any attached accelerators supplied with data. Its new SP7 socket exposes up to 16 memory channels per socket, for roughly 1.6 TB/s of aggregate memory bandwidth.
AMD also says Venice doubles CPU-to-GPU bandwidth over today's platform, which almost certainly comes from adding PCIe 6.0 and its higher per-lane throughput.
