THE BIG PICTURE: With memory prices skyrocketing, tech companies are exploring new ways to reduce the cost of AI development. Earlier this year, Google detailed its TurboQuant compression technique, which reportedly reduces LLM memory usage by up to 6×. Now, researchers in Belgium have developed a NAND-DRAM hybrid architecture that they claim could significantly lower AI inference costs in the future.

Leuven, Belgium-based nanotechnology and semiconductor research center Imec has unveiled what it describes as the world's first 3D implementation of a charge-coupled device (CCD) designed for AI memory applications. The new technology combines the speed of DRAM with the storage density of NAND flash, potentially reducing the "memory wall" bottleneck, in which limited memory bandwidth forces AI accelerators to wait for data instead of processing tokens continuously.

The device is built by stacking memory chips vertically rather than placing them side by side, enabling ultra-fast charge transfer speeds reportedly exceeding 4GHz under laboratory conditions. To reduce leakage and support denser 3D integration, the researchers used indium gallium zinc oxide (IGZO), a compound that offers significantly better electron mobility, energy efficiency, and optical transparency than traditional silicon.